X86 and ARM Call Convention
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ARM64 call convention
/* ARM64 Runtime register usage conventions. r0 : w0 is 32-bit return register and x0 is 64-bit. r0-r7 : Argument registers. r8-r15 : Caller save registers (used as temporary registers). r16-r17: Also known as ip0-ip1, respectively. Used as scratch registers by the linker, by the trampolines and other stubs (the backend uses these as temporary registers). r18 : Caller save register (used as temporary register). r19 : Pointer to thread-local storage. r20-r29: Callee save registers. r30 : (lr) is reserved (the link register). rsp : (sp) is reserved (the stack pointer). rzr : (zr) is reserved (the zero register). Floating-point registers v0-v31 v0 : s0 is return register for singles (32-bit) and d0 for doubles (64-bit). This is analogous to the C/C++ (hard-float) calling convention. v0-v7 : Floating-point argument registers in both Dalvik and C/C++ conventions. Also used as temporary and codegen scratch registers. v0-v7 and v16-v31 : trashed across C calls. v8-v15 : bottom 64-bits preserved across C calls (d8-d15 are preserved). v16-v31: Used as codegen temp/scratch. v8-v15 : Can be used for promotion. Must maintain 16-byte stack alignment. Mterp notes: The following registers have fixed assignments: reg nick purpose x20 xPC interpreted program counter, used for fetching instructions x21 xFP interpreted frame pointer, used for accessing locals and args x22 xSELF self (Thread) pointer x23 xINST first 16-bit code unit of current instruction x24 xIBASE interpreted instruction base pointer, used for computed goto x25 xREFS base of object references in shadow frame (ideally, we'll get rid of this later). x26 wPROFILE jit profile hotness countdown x16 ip scratch reg x17 ip2 scratch reg (used by macros) Macros are provided for common operations. They MUST NOT alter unspecified registers or condition codes. */ -
ARM call convention
/* ARM EABI general notes: r0-r3 hold first 4 args to a method; they are not preserved across method calls r4-r8 are available for general use r9 is given special treatment in some situations, but not for us r10 (sl) seems to be generally available r11 (fp) is used by gcc (unless -fomit-frame-pointer is set) r12 (ip) is scratch -- not preserved across method calls r13 (sp) should be managed carefully in case a signal arrives r14 (lr) must be preserved r15 (pc) can be tinkered with directly r0 holds returns of <= 4 bytes r0-r1 hold returns of 8 bytes, low word in r0 Callee must save/restore r4+ (except r12) if it modifies them. If VFP is present, registers s16-s31 (a/k/a d8-d15, a/k/a q4-q7) must be preserved, s0-s15 (d0-d7, q0-a3) do not need to be. Stack is "full descending". Only the arguments that don't fit in the first 4 registers are placed on the stack. "sp" points at the first stacked argument (i.e. the 5th arg). VFP: single-precision results in s0, double-precision results in d0. In the EABI, "sp" must be 64-bit aligned on entry to a function, and any 64-bit quantities (long long, double) must be 64-bit aligned. */ -
X86 call convention
/* x86 ABI general notes: Caller save set: eax, edx, ecx, st(0)-st(7) Callee save set: ebx, esi, edi, ebp Return regs: 32-bit in eax 64-bit in edx:eax (low-order 32 in eax) fp on top of fp stack st(0) Parameters passed on stack, pushed right-to-left. On entry to target, first parm is at 4(%esp). Traditional entry code is: functEntry: push %ebp # save old frame pointer mov %ebp,%esp # establish new frame pointer sub FrameSize,%esp # Allocate storage for spill, locals & outs Once past the prologue, arguments are referenced at ((argno + 2)*4)(%ebp) Stack must be 16-byte aligned to support SSE in native code. If we're not doing variable stack allocation (alloca), the frame pointer can be eliminated and all arg references adjusted to be esp relative. */ -
X86_64 call convention
/* x86_64 ABI general notes: Caller save set: rax, rdx, rcx, rsi, rdi, r8-r11, st(0)-st(7) Callee save set: rbx, rbp, r12-r15 Return regs: 32-bit in eax 64-bit in rax fp on xmm0 First 8 fp parameters came in xmm0-xmm7. First 6 non-fp parameters came in rdi, rsi, rdx, rcx, r8, r9. Other parameters passed on stack, pushed right-to-left. On entry to target, first param is at 8(%esp). Traditional entry code is: Stack must be 16-byte aligned to support SSE in native code. If we're not doing variable stack allocation (alloca), the frame pointer can be eliminated and all arg references adjusted to be esp relative. */